| Title | : | Efficient Last Level Caching in Multi-Core Systems |
| Speaker | : | Adhar Dua (IITM) |
| Details | : | Thu, 27 Jun, 2024 4:00 PM @ SSB 233 |
| Abstract: | : | Multi-core systems enable concurrent operation of diverse applications with varying memory requirements. However, the interference between data mapped to the Last Level Cache (LLC) from different cores can be detrimental. This interference often results in premature eviction and thrashing, leading to reduced system throughput. Performance can be significantly enhanced by maintaining the working set of applications that can fit within the cache, while also allocating cache space for parts of the working set from remaining applications. We introduce a novel, application-aware, coarse-grained cache replacement policy named Address Translation Aware Re-reference Interval Prediction (ATARRIP). This policy incorporates a newly defined metric, High Reuse Distance (HRD) pages, calculated during the address translation phase. We employ the HRD pages metric to predict application behavior, thereby refining our cache replacement decisions. Our empirical findings indicate that ATARRIP surpasses the previously established state-of-the-art coarse-grained policy for multi-core systems, TADRRIP, in multi-core systems both with and without prefetchers. Additionally, ATARRIP achieves performance comparable to some fine-grained policies such as SHIP, and is only marginally outperformed by others like Hawkeye. ATARRIP managed shared cache achieves significant improvements over SRRIP on both 4-core and 8-core systems, with approximately half the storage overhead compared to the traditional LRU policy for a 16-way set associative LLC. |
