| Title | : | Hardware enforced security for memory and branch predictors |
| Speaker | : | Krishnakumar Gnanambikai (IITM) |
| Details | : | Wed, 1 May, 2024 10:00 AM @ By Google Meet |
| Abstract: | : | With the advent of FPGAs, microprocessors are no longer rigid in design but have transformed into a customizable, re-programmable entity, that can be customized to the needs of the deployment environment. This flexibility in system design can be utilized to incorporate several custom features. Security is one such feature that plays a crucial role in the modern era of connected devices. Ever since the era of the Internet began, the number of security breaches across computers worldwide has increased enormously. Deploying countermeasures for security threats in the hardware promises to be more efficient than the software-only counterparts. This thesis begins with a survey of the security features incorporated in hardware over the last five decades. We observe that two categories of security vulnerabilities have gained recurring attention over the years. They are, what we term as Memory vulnerabilities and Micro-architecture based vulnerabilities. Around 47% of the total works surveyed deal with Memory vulnerabilities, while around 25% of them deal with Micro-architecture based vulnerabilities. Common Weakness Enumeration (CWE), a forum that ranks security threats, ranks Memory Vulnerability and Micro-Architecture based vulnerabilities among the top ten software and hardware weaknesses respectively. In this thesis, we present countermeasures for attacks from each of the two categories. We propose a framework to analyze micro-architecture based vulnerabilities over branch predictors and establish a tuneable scheme of defense to satisfy the orthogonal constraints of security and performance. In the later part of the thesis, we present solutions that thwart memory vulnerabilities that arise out of unsafe coding practices in languages such as C and C++. Our comprehensive solution for memory vulnerabilities exhibits very low performance and area overheads. All our solutions are implemented on open-source processors and verified on FPGA platforms. Web Conference Link : https://meet.google.com/sij-jpdv-rex |
