| Title | : | Multicore processors with simpler coherence |
| Speaker | : | Kambhammettu Sri Satya Sudhanva (IITM) |
| Details | : | Wed, 5 Jul, 2023 11:30 AM @ Google Meet |
| Abstract: | : | Multicore processors have become the de facto standard in today’s world for most applications. One of the key factors involved in the correct functioning of these processors is cache coherence. When multiple cores attempt to access the same block of data, it ensures that the data perceived by each core remains coherent with the data perceived by other cores i.e., single-writer-multiple-readers invariant and data-value invariant are enforced. However, designing high performance coherence protocols that are correct is a challenging task due to the presence of numerous transient states as well as the races that could occur in each of these states. Also, the effort involved in verifying these is not trivial due to the large number of transitions involved. A simple solution to avoid cache coherence is by having shared L1 caches amongst the cores. While it does get rid of the requirement for coherence, latency increases for all the accesses. We analyse memory sharing pattern across cores for various benchmarks and evaluate the performance of different shared L1 cache hierarchies against those based on traditional coherence protocols. Relying on these results, a new shared L1 cache hierarchy is proposed to achieve a balance between the performance of the system and design complexity of the cache hierarchy. Web Conference Link :https://meet.google.com/gvu-wxkc-fsg |
