Department of Computer Science & Engineering

This talk will be about two recent works on hardware prefetching:

(i) Bouquet of instruction pointers, an L1 data prefetching technique that outperforms the state-of-the-art data prefetchers. We propose an instruction pointer classifier based hardware prefetching technique for the DPC-3. We use multiple instruction pointer based prefetchers that suit different access patterns and overall cover a wide spectrum of access patterns. Our classifier classifies instruction pointers at the L1 cache level and communicates the same to the L2 prefetcher. Our prefetching framework named Instruction Pointer Classifier based Prefetching (IPCP) provides 43.75% improvement for single-core and 22% for 25 selectively chosen multi-core mixes, respectively. IPCP demands a hardware overhead of 16.7KB per core.

(ii) A hardware prefetcher that can fool a cross-core side-channel attacker at the shared last-level cache. The fundamental principle behind all the cross-core eviction attack strategies is that the attacker can observe LLC access time differences (in terms of latency differences between events such as hits/misses) to infer about the data used by the victim. We fool the attacker (by providing LLC hits to the addresses of interest) through a back-invalidation-hits triggered hardware prefetching technique (BITP). BITP is an L2 cache level hardware prefetcher that prefetches the back-invalidated block addresses and refills the LLC (along with the L2) before the attacker’s observation/access, efficiently nullifying inferences due to differences in LLC access latencies.

Bio: Biswabandan Panda is an Assistant Professor at the CSE dept. of IIT Kanpur. Prior to that, he was at the PACAP team of INRIA, Rennes, working with André Seznec. He received his Ph.D. and Masters from Indian Institute of Technology Madras. His area of research includes performance and security issues related to memory systems.