| Title | : | Endurance Enhancement of Write-Optimized STT-RAM Caches |
| Speaker | : | Puneet Saraf (IITM) |
| Details | : | Fri, 31 May, 2019 11:00 AM @ A M Turing Hall |
| Abstract: | : | Low density and high leakage power of SRAM are the major setbacks for its scalability. Non-volatile memory (NVM) like spin-transfer torque random access memory (STT-RAM) is a suitable replacement for SRAM at the last level cache (LLC). NVM offers high density, and near zero leakage, which are highly desired for on-chip caches. A few drawbacks of STT-RAM such as high write latency and limited endurance, have to be taken care before it can replace SRAM at the LLC. The high write latency is because of the high current required for a write operation compared to a read operation. The endurance value of STT-RAM indicates the number of write operations that can be performed before it can lead to failure. Endurance can further degrade due to the non-uniform write accesses across the STT-RAM cache. Prior works have either tried to optimize the write latency or endurance.
In this talk, by considering write-optimized STT-RAM, we propose endurance improvement techniques by changing the address mapping at STT-RAM LLC combined with a family of replacement policies. Endurance enhancement of STT-RAM is achieved by reducing the peak number of writes, global write variation, and the average number of writes. Write optimization of STT-RAM may lead to lower retention time. We take care of low retention time of write-optimized STT-RAMs using a refresh mechanism. We employ refresh-aware cache replacement policy wherein the cache blocks that are about to expire are preferred to the recently refreshed cache blocks. This refresh-aware policy, when combined with the recency information of the cache blocks, enhances both performance and endurance of STT-RAM LLC. We show that the lifetime of STT-RAM LLC is improved significantly compared to STT-RAM with no wear leveling. |
