| Title | : | Flexible DFD hardware for efficient post-silicon validation and its versatile reuses |
| Speaker | : | Sandeep Chandran (AMD) |
| Details | : | Fri, 11 May, 2018 11:00 AM @ A M Turing Hall |
| Abstract: | : | An increasing number of functional errors are escaping into silicon as conventional pre-silicon verification techniques do not scale well with increasing design complexity. Therefore, modern architectures now include elaborate Design-for-Debug (DFD) hardware to increase visibility into internal functioning of the chip that is crucial to debugging such errors. In the first part of this talk, I will discuss a programmable DFD hardware that checks whether temporal relationships between events of interest specified by the validation engineer hold over an execution trace and triggers suitable action in response to such event sequences in a timely manner. The resulting improvements in efficiency of post-silicon debug is highlighted through four case studies that are inspired by actual bugs encountered in the industry. In the second part of the talk, I will discuss how this programmability can be exploited by applications in novel ways in-field, to enhance overall system performance. This is demonstrated by reusing the DFD hardware to mitigate operating system jitter, which is the variation in execution time induced due to activity of the operating system, that affects high-performance, soft real-time systems.
Bio: Sandeep Chandran is a performance architect in the Cores division of AMD where he is responsible for performance modeling of the floating-point and SIMD unit. Previously, he completed his PhD from IIT Delhi and his bachelors from Visveswaraya Technological University. His research interests are broadly in the areas of computer architecture and post-silicon validation. He was among the early recipients of the TCS research fellowship. His works have been showcased at various industry forums such as TCS Sangam 2014, and AMD Asia Technical Conference 2017. One of his works was a Best Paper Award candidate at ASP-DAC 2016. |
