| Title | : | Post Silicon Validation |
| Speaker | : | Sandeep Chandran (AMD, Bangalore.) |
| Details | : | Mon, 8 May, 2017 10:00 AM @ BSB 361 |
| Abstract: | : | Growing complexity of modern System-on-chips (SoCs) have rendered conventional pre-silicon
verification techniques inadequate, as a result of which, an increasing number of functional errors
are escaping into silicon. Modern architectures now include elaborate post-silicon validation
mechanisms to increase the visibility into internal functioning of a chip which is crucial to debugging such errors. In this talk, I will discuss key constraints under which these mechanisms operate, the inefficiencies in the state-of-the-art mechanisms, and techniques that we have proposed to significantly improve the efficiency of debug. I will conclude by presenting some early results on how the hardware used to gain visibility into the chip can outlive its purpose by assuming new roles to help user applications enhance their overall performance.
Speaker Bio: Sandeep Chandran is currently working as a Senior Design Engineer, Cores - Performance Modeling, at AMD India Pvt Ltd., Bangalore, where he joined in May 2016.. Prior to joining AMD, he was a full-time PhD student at the Dept of CSE, IIT Delhi (where he joined for the MTech program in 2010, and converted it to PhD program). He was guided Prof. Preeti Ranjan Panda, and Prof. Smruti R Sarangi in the area of post-silicon validation. He also interned at Freescale semiconductors, Noida in the silicon bring-up team for 6 months during his PhD. His research has been published in multiple IEEE Transactions, and at several other leading conferences such as DATE and ASP-DAC (where his paper was a Best-paper award candidate). |
