| Title | : | An ADD based Chisel Compiler with reduced Syntactic Variance |
| Speaker | : | Vikas Chauhan (IITM) |
| Details | : | Tue, 24 May, 2016 3:00 PM @ BSB 361 |
| Abstract: | : | The need for quick design space exploration and higher abstracted features required to design complex circuits has led designers to adopt High Level Synthesis languages (HLS) for hardware generation. Chisel is one such language, which offers majority of the abstraction facilities found in today’s software languages and also guarantees synthesizability of the generated hardware. However, most of the HLS languages, including Chisel, suffer from syntactic variance and thus the hardware inferred by these languages are inconsistent and rely heavily on the description styles used by the designer. Thus semantically equivalent circuit descriptions with different syntax can lead to different hardware utilization. In this paper, we propose the use of ADDs (Assignment Decision Diagrams) as an intermediate representation between Chisel and the target netlist representation. Following this path we have shown that for a given design, two different styles of Chisel implementations yield the same target netlist, thereby ensuring syntactic invariance. For the same design implementations the conventional Chisel compiler reports significant syntactic variance. In addition, we show empirically that the netlist generated by the proposed technique is equally competitive to the most optimal netlist generated by the conventional compiler while targeting an FPGA, implying that different implementations leads to close to optimal solutions. |
