| Title | : | CAD techniques for soft-error-robust design with minimal area impact |
| Speaker | : | Pavan Vithal Torvi (IITM) |
| Details | : | Tue, 12 Apr, 2016 2:00 PM @ BSB 361 |
| Abstract: | : | The advancements in semiconductor manufacturing have reduced the component size, resulting in lower area and/or lower power with better performance, compared to the ICs (Integrated Circuits) manufactured in the older technologies. These improvements have helped IC designers to include more features in the ICs by increasing the transistor count, without increasing the IC cost significantly. The availability of increased set of features at lower power, higher speed and at the same cost has accelerated the penetration of ICs in several systems, some of which are safety critical. The safety critical systems are expected to work reliably and fault-free over a wide range of operating conditions. Soft-errors are transient errors that can cause a system to malfunction. A soft-error occurs when a highly energetic particle strikes the semiconductor and penetrates into it. The reduced component sizes have reduced the charge required to flip the voltage value at a node, making the ICs manufactured in newer processes more vulnerable. Further, with larger number of transistors in the ICs, the probability of the soft-error failures has become significant. It was observed that the contribution of the sequential elements to the design level soft-error failures is significant and is expected to be more than the memory contribution in future. Therefore, mitigating the effects of the the soft-errors on the sequential elements is essential. In this work, we discuss methods to make the ICs robust to soft-errors by selectively hardening the sequential elements. Two approaches are discussed: in the first approach, we swap the flip-flops that are critical to the correct functioning of the system by radiation hardened flip-flops; and, in the second approach, we increase the delay of the timing paths between flip-flops, such that the probability of a spurious transition at a flip-flop due to soft-error getting latched in the subsequent flip-flop is reduced. The flows proposed are at the layout stage and they consider the overheads while optimizing the design for soft-error robustness. The flows are evaluated on two designs used in the industrial System-on-Chips (SoC). On one of the two designs, with the flip-flop swap approach, we observe a reduction of 36% in sequential soft-error-rate contribution for an increase of 9% sequential cell area. |
