Selective Memory Compression for GPU Memory Oversubscription Management.
Abdun Nihaal, Madhu Mutyam
Appeared in
Proceedings of the 53rd International Conference on Parallel Processing, ICPP 2024, Gotland, Sweden, August 12-15, 2024 (ICPP 2024),
Vol , No., pp.189-198, Aug 2024.
Cache Line Pinning for Mitigating Row Hammer Attack.
Praseetha M, Madhu Mutyam, Venkata Kalyan Tavva
Appeared in
Proceedings of the 53rd International Conference on Parallel Processing, ICPP 2024, Gotland, Sweden, August 12-15, 2024 (ICPP 2024),
Vol , No., pp.802-811, Aug 2024.
Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD.
Endurance enhancement of write-optimized STT-RAM caches.
Puneet Saraf, Madhu Mutyam
Appeared in
Proceedings of the International Symposium on Memory Systems, MEMSYS 2019, Washington, DC, USA, September 30 - October 03, 2019. (MEMSYS 2019),
pp.101-113, Oct 2019.
POSTER: Variable Sized Cache-Block Compaction.
Sayantan Ray, Madhu Mutyam
Appeared in
28th International Conference on Parallel Architectures and Compilation Techniques, PACT 2019, Seattle, WA, USA, September 23-26, 2019 (PACT 2019),
pp.471-472, Sep 2019.
Formal Modeling and Verification of a Victim DRAM Cache.
S. R. Swamy Saranam, Madhu Mutyam
Appeared in
2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018 (ISVLSI 2018),
pp.88-93, Jul 2018.
Formal Modeling and Verification of Controllers for a Family of DRAM Caches.
FatCBST: Concurrent Binary Search Tree with Fatnodes.
Praveen Alapati, Venkata Kalyan Tavva, Madhu Mutyam
Appeared in
19th IEEE International Conference on High Performance Computing and Communications; 15th IEEE International Conference on Smart City; 3rd IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2017, Bangkok, Thailand, December 18-20, 2017,
pp.356-363, Dec 2017.
RCTP: Region Correlated Temporal Prefetcher.
Dennis Antony Varkey, Biswabandan Panda, Madhu Mutyam
Appeared in
2017 IEEE International Conference on Computer Design, ICCD 2017, Boston, MA, USA, November 5-8, 2017 (ICCD 2017),
pp.73-80, Nov 2017.
Praveen Alapati, Chongala .S.R.Swamy Saranam, Madhu Mutyam
Appeared in
Algorithms and Architectures for Parallel Processing - 17th International Conference, ICA3PP 2017, Helsinki, Finland, August 21-23, 2017, Proceedings,
Lecture Notes in Computer Science, Vol 10393, pp.776-790, Aug 2017.
An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors.
Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
Appeared in
30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, VLSID 2017, Hyderabad, India, January 7-11, 2017 (VLSID 2017),
pp.35-40, Jan 2017.
SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache.
Pritam Majumder, T. Venkata Kalyan, Madhu Mutyam
Appeared in
32nd IEEE International Conference on Computer Design, ICCD 2014, Seoul, South Korea, October 19-22, 2014 (ICCD 2014),
pp.104-109, Oct 2014.
Using packet information for efficient communication in NoCs.
Prasanna Venkatesh Rengasamy, Madhu Mutyam
Appeared in
Eighth IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Ferrara, Italy, September 17-19, 2014,
pp.143-150, Sep 2014.
Data remapping for an energy efficient burst chop in DRAM memory systems.
Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time.
T. Venkata Kalyan, Ravi Kasha, Madhu Mutyam
Appeared in
19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, January 20-23, 2014,
pp.598-603, Jan 2014.
Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs.
John Jose, Madhu Mutyam
Appeared in
ACM Trans. Design Autom. Electr. Syst.,
Vol 19, pp.35:1-35:22, 2014.
EFGR: An Enhanced Fine Granularity Refresh Feature for High-Performance DDR4 DRAM Devices.
SLIDER: Smart Late Injection DEflection Router for mesh NoCs.
Bhawna Nayak, John Jose, Madhu Mutyam
Appeared in
2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013 (ICCD 2013),
pp.377-383, Oct 2013.
DeBAR: deflection based adaptive router with minimal buffering.
An Application-Aware Cache Replacement Policy for Last-Level Caches.
Tripti S. Warrier, B. Anupama, Madhu Mutyam
Appeared in
Architecture of Computing Systems - ARCS 2013 - 26th International Conference, Prague, Czech Republic, February 19-22, 2013. Proceedings (ARCS 2013),
Lecture Notes in Computer Science, Vol 7767, pp.207-219, Feb 2013.
Prevention slot flow-control mechanism for low latency torus network-on-chip.
TRACKER: A low overhead adaptive NoC router with load balancing selection strategy.
John Jose, K. V. Mahathi, J. Shiva Shankar, Madhu Mutyam
Appeared in
2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012 (ICCAD 2012),
pp.564-568, Nov 2012.
SkipCache: miss-rate aware cache management.
Raghavendra, Tripti S. Warrier, Madhu Mutyam
Appeared in
International Conference on Parallel Architectures and Compilation Techniques, PACT '12, Minneapolis, MN, USA - September 19 - 23, 2012,
pp.481-482, Sep 2012.
Prevention flow-control for low latency torus networks-on-chip.
Arpit Joshi, Madhu Mutyam
Appeared in
NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011 (NOCS 2011),
pp.41-48, May 2011.
Timing variation-aware scheduling and resource binding in high-level synthesis.
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