Lab Details

PACE Lab : Programming Languages, Architecture, Compilers Education LaboratoryLink to Lab Webpage

Research Areas	Memory System Design, Network-on-chip architectures, Cache Design in Multicore, Program Analysis, Parallelization, Code Optimization.
Members	Faculty : Madhu Mutyam, Kartik Nagar, V. Krishna Nandivada, Rupesh Nasre. Students/Scholars : . PhD : Gnaneswara Rao J, Aman Nougrahiya, Jyothi Krishna V S, Chongala .S.R.Swamy Saranam, Somesh Singh, Somesh Singh, Shouvick Mondal, Anju M A, Kasaraneni Ramya, Vimala S, Sheera Shamsu. MS : Nizamudheen Ahmed, Shashidhar G, Rakesh Patil, Dennis Antony Varkey, Aman Sharma, Sayantan Ray, Arun T, Joe Augustine, Rajendra Kumar Dangwal, Diptanshu Kakwani, Adhar Dua. M.Tech : Manoj Gangadhar Dongare. B.Tech(DD) : Anirudh S. Project Staffs :
Recent Publications	Cache Line Pinning for Mitigating Row Hammer Attack. Praseetha M , Madhu Mutyam , Venkata Kalyan Tavva Appeared in Proceedings of the 53rd International Conference on Parallel Processing, ICPP 2024, Gotland, Sweden, August 12-15, 2024, Vol , No., pp.802-811, Aug 2024 Selective Memory Compression for GPU Memory Oversubscription Management. Abdun Nihaal , Madhu Mutyam Appeared in Proceedings of the 53rd International Conference on Parallel Processing, ICPP 2024, Gotland, Sweden, August 12-15, 2024, Vol , No., pp.189-198, Aug 2024 FlexiGran: Flexible Granularity Locking in Hierarchies. Anju Mongandampulath Akathoott , Rupesh Nasre Appeared in Euro-Par 2024: Parallel Processing - 30th European Conference on Parallel and Distributed Processing, Madrid, Spain, August 26-30, 2024, Proceedings, Part I, Lecture Notes in Computer Science, Vol 14801, No., pp.3-17, Aug 2024 COWS for High Performance: Cost Aware Work Stealing for Irregular Parallel Loop. Prasoon Mishra , V. Krishna Nandivada Appeared in ACM Trans. Archit. Code Optim., Vol 21, pp.12:1-12:26, Jan 2024 Meerkat: A Framework for Dynamic Graph Algorithms on GPUs. Kevin Jude Concessao , Unnikrishnan Cheramangalath , MJ Ricky Dev , Rupesh Nasre Appeared in Int. J. Parallel Program., Vol 52, No., pp.400-453, Jan 2024
Sponsored Projects	Dynamic Graph Algorithms on ManyÂcores (Funding Agency :IITM-ERP) Formal Verification and Synthesis of Secure Designs. (Funding Agency :NFSG) Exploring Techniques to Optimize Main Memory of Multi-Core Systems (Funding Agency :DST) IBM Shared University Research Grant (Funding Agency :IBM-SURG) Research funding from Board of Research in Nuclear Sciences (Funding Agency :DAE)

Department of Computer Science & Engineering

Indian Institute of Technology Madras, Chennai, India.