Department of Computer Science & Engineering

VLSI Lab : VLSI LaboratoryLink to Lab Webpage

This lab is a part of the RISE group.

Research Areas	Software Aspects, Design Automation, Network Security, Digital VLSI, Formal Design Verification.
Members	Faculty : V. Kamakoti, Pratyush Kumar, Chester Rebeiro. Students/Scholars : Project Staffs :
Recent Publications	WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors.          Pallavi Borkar , Chen Chen , Mohamadreza Rostami , Nikhilesh Singh , Rahul Kande , Ahmad-Reza Sadeghi , Chester Rebeiro , Jeyavijayan Rajendran       Appeared in 33rd USENIX Security Symposium, USENIX Security 2024, Philadelphia, PA, USA, August 14-16, 2024, Vol , No., Aug 2024 Secure Compiler Framework to Design Fault Attack Resistant Software.          Keerthi K. , Chester Rebeiro       Appeared in 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2023 - Supplemental Volume, Porto, Portugal, June 27-30, 2023, pp.206-208, Jun 2023 YODA: Covert Communication Channel over Public DNS Resolvers.          Sandip Saha , Sareena Karapoola , Chester Rebeiro , V. Kamakoti       Appeared in 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Network, DSN 2023, Porto, Portugal, June 27-30, 2023, pp.252-260, Jun 2023 FaultMeter: Quantitative Fault Attack Assessment of Block Cipher Software.          Keerthi K. , Chester Rebeiro       Appeared in IACR Trans. Cryptogr. Hardw. Embed. Syst., Vol 2023, pp.212-240, Jan 2023 SIGNED: A Challenge-Response Scheme for Electronic Hardware Watermarking.          Patanjali SLPSK , Abhishek Anil Nair , Chester Rebeiro , Swarup Bhunia       Appeared in IEEE Trans. Computers, Vol 72, pp.1763-1777, Jan 2023
Sponsored Projects	A Formally Verified Multi-precision Arithmetic Library for Cryptographic Applications. (Funding Agency :CAIR) Formal Methods for Reliable Safety-Critical System Design (Funding Agency :NFIG)