Department of Computer Science & Engineering

Description:

To provide detailed discussion on processor microarchitectural vulnerabilities and measures to mitigate them.

Course Content:

Processor Microarchitecture, Memory hierarchy, Out-of-order execution, Branch prediction, Speculative execution, Prefetching, Superscalar processors, Multithreaded Processors, Multi-core Processors. Timing Attacks, Side-channel attacks, Covert-channel attacks, Cache timing attack models, Prime-and-Probe, Flush-and-Reload, Flush-and-Flush, Evict-and-Time, Cache Collision, Out-of-order execution timing attack – Meltdown, Speculative execution attack – Spectre, Hardware prefetch-aided timing channel attacks. Secure Memory Components – Timing attacks on memory components -- cache, main memory, memory controllers, translation look-aside buffers (TLBs), Coherence directories; Secure cache architectures, Secure cache coherence directories, Secure TLBs, Secure memory controller designs, Mitigating memory bus side channel attack, Exploiting hardware prefetching to mitigate cache timing attacks. Defending Speculative Execution Attacks – Timing attacks in speculative execution processors, Techniques to mitigate speculative execution attacks, Timing attacks on branch prediction units (BPUs), Secure BPUs.

TextBooks:

Papers from the top-rated conferences: ISCA, HPCA, MICRO, ASPLOS, USENIX Security.

ReferenceBooks:

Papers from the top-rated conferences: ISCA, HPCA, MICRO, ASPLOS, USENIX Security.